International Journal of
Science and Technology Education Research

  • Abbreviation: Int. J. Sci. Technol. Educ. Res.
  • Language: English
  • ISSN: 2141-6559
  • DOI: 10.5897/IJSTER
  • Start Year: 2010
  • Published Articles: 79

Full Length Research Paper

Vanishing of clock power consumption by using provisional pulse enhancement scheme

A. Saisudheer
  • A. Saisudheer
  • M. Tech (vlsisd), Tirupathi, India
  • Google Scholar


  •  Received: 15 August 2013
  •  Accepted: 07 July 2014
  •  Published: 29 September 2014

References

Yin-Tsung Hwang, Jin-Fa Lin, and Ming- Hwasheu, yin-Tsung Hwang, Jin-Fa Lin, And Ming-Hwasheu Manuscript (2010). "Low power pulse triggered flip flop design with conditional pulse enhancement scheme" received April 24,2010; revised August 12,2010 and November 13, 2010; accepted November 16, 2010.Date of publication January 06, 2011; date of current version January 18, 2012.

 

Mahmoodi H, Tirumalashetty V, Cooke M, Roy K (2009). "Ultra low power clocking scheme using energy recovery and clock gating," IEEE Trans. Very Large Scale Integer. (VLSI) Syst. 17:33–44
Crossref

 

Teh CK, Hamada M, Fujita T, Hara H, Ikumi N, Oowaki Y (2006). "Conditional data mapping flip-flops for low power and high-performance systems," IEEE Trans. Very Large Scale Integer. (VLSI) Systems.14:1379–1383.

 

Shu YH, Enqchen ST, Sun MC, Feng WS (2006). "XNOR-based double-edge-triggered flip-flop for two-phase pipelines," IEEE Trans. Circuits Syst. II, Exp. Briefs. 53(2):138–142
Crossref

 

Rasouli SH, Khademzadeh A, Afzali-Kusha A, Nourani M (2005). " Low power single- and double-edge-triggered flip-flops for high speed applications," Proc. Inst. Electr. Eng.—Circuits Devices Syst. 152(2):118–122.
Crossref

 

Zhao P, Darwish T, Bayoumi M (2004). "High-performance and low power conditional discharge flip-flop," IEEE Trans. Very Large Scale Integer. (VLSI) Syst.. 12(5):477–484.
Crossref